This invention relates to input/output (I/O) interfaces used for connecting relatively complex and high capacity computer systems to peripheral equipment. More particularly, the present invention relates to a new and improved I/O interface by which to send and receive communication signals, preferably in a serial or narrow parallel form, which offers the advantage of relatively small size, relatively high performance, relatively low power consumption, and comparatively great versatility and flexibility in accommodating and executing a variety of different complex communication protocols.
Many modern electronic devices are built as an entire system on a single semiconductor chip, and as such, are known as system on a chip (SoC) integrated circuits or application specific standard products (ASSPs). Building an entire system or large portion of the system on a single chip has a number of advantages. Although the costs of initially designing and fabricating the component may be relatively high, it is very inexpensive to replicate large numbers of the systems, thereby reducing the cost of the system on a per unit basis. By designing the entire system or large portion of the system on a single chip, a high level of functionality and better functional interaction between the components of the system usually results in a more reliable and better functioning product. Usually the entire system or large portion of the system may be fabricated and packaged in an electronic component which is physically very small, making such SoCs and ASSPs ideal for use in small and portable devices which require a relatively high level of functionality, such as portable telephones.
Disadvantages of such entire system SoCs and ASSPs is that they are usually specifically designed to have a single, fixed function. With the continuing evolution of improvements in electronic devices, a fixed function system on a chip is likely to have a relatively short usable lifetime before its functionality becomes outmoded due to the progress of improvements and changes in technology. Very few, if any, improvements may be accommodated in a fixed function chip because it has been specifically designed to implement only a single set of functionality. Its fixed functionality usually does not anticipate future improvements because such future improvements are generally not predictable. In order to implement improvements in such systems, it is necessary to redesign the entire semiconductor chip, which again introduces the relatively high costs of designing and preparing for fabrication of the system on a semiconductor chip.
Attempts at making systems on a chip more flexible in terms of accommodating more than a single fixed functionality have been made, but such attempts involve many complexities. Attempting to determine exactly the mix of the different components needed on such a chip, such as a processor core, memory, logic gates and peripheral interface devices is very difficult to predict because different devices require different quantities of these components and functionality from these components. Efforts to provide great flexibility in terms of quantity and capabilities generally translates into building more of these components to have reserve quantity and excess functionality available. Increasing the number of components on the chip may not be possible, because of the limited size of the chip upon which to form these components. Increasing the number of components on a chip also increases the cost of fabricating the chip.
These considerations are particularly relevant to input/output (I/O) interfaces which are included on such SoCs and ASSPs with increasing regularity. Traditional hard-wired, I/O interfaces are subject to the restrictions of fixed functionality and limited flexibility to accommodate future improvements.
An increasingly popular alternative which provides maximum flexibility is an I/O interface which communicates the signals directly to a register, and an embedded controller connected to that register which executes firmware in accordance with the communication protocol. New or different functionality may be achieved by loading new firmware onto the embedded controller. The disadvantage of this approach is that the clocking rates must generally be many times the rate of the input/output signals, for example a factor of 8 to 32 times greater. With the increases in modern signal communication rates, the internal clock rates necessary to implement this functionality become impractical to achieve, in many circumstances. Moreover in those devices which are portable and operate from self-contained limited power sources such as batteries, the fact that in most modern logic families power consumption increases directly in proportion to the clock rate, the need to use higher clock rates reduces the time for using such devices between recharging. Many devices such as portable telephones and wireless data network adapters depend on having a relatively long usable lifetime between recharging cycles.
Another approach to flexibility is to use programmable logic in the form of field programmable gate arrays (FPGAs). The logic of such FPGAs is programmed as a result of loading a particular control pattern into the chip after it is fabricated. Changing the control pattern permits changing the functionality of the device. The disadvantage of this FPGA approach is that it tends to be significantly less cost-effective, especially for ASSPs and other high-volume production items. Moreover, to insure enough functionality from an FPGA, the number of logic components are typically greater than is actually necessary, typically by a factor of 10 sometimes by as much as a factor of up to 100. Therefore an FPGA will usually consume more space on the SoC than is necessary. Furthermore, it is often difficult to mix FPGAs and blocks of hard wired logic or processor cores on the same chip. FPGAs may offer some benefits, the approach is generally not an ideal solution for all I/O interfaces, nor for power-limited applications.
In all of these cases, the primary nature of a typical I/O interface is a multiplexed serial interface that is either a single data signal or a small number of parallel data signals, which carry larger amounts of data in time sequence. The small number of data signals are often used along with a data transfer clock signal and 1 to 3 other discrete logic signals to perform ancillary functions such as device selection or data direction control. Coding information accompanies these signals and provides control to indicate how the recipient should interpret the received signals. The protocol or rules which govern this sequential transfer may be defined by the behavior of an extended finite state machine. The behavior of a finite state machine can be transformed into a set of logic equations which implement an instance of the communication protocol. The functionality of the state machine depends upon executing commands which set up the various functional states involved in I/O communication. Because of the ability to emulate finite state machines with an embedded processor, it is common to implement I/O protocol control using using firmware on the embedded processor.
Interfaces of this nature are widely used in a variety of applications. For example, the interface may be part of a system chip used in a wireless telephone communication transceiver, in which the system chip acts as both a receiver for incoming signals and a source of outgoing signals to be broadcast. Other examples of similar applications of interfaces are at the opposite ends of a communication link in disk drives, tape drives, wide area networks and local area networks.
In addition, there are a large number of short haul serial buses which are used for communicating signals between separate integrated circuit chips in an electronic device. One type is used in conjunction with external exposed bus, an example of which is the well-known universal serial bus (USB) which is used primarily for connecting a keyboard, mouse and other peripherals to a personal computers. There are many other type of short haul serial bus is used primarily for interconnecting chips within an electronic device. If the signaling between chips can proceed at an acceptable speed, it is an advantage to serialize the signals and send them over a small number of conductors. Reducing the number of conductors to connect signals between the chips saves money and reduces the size of the components, because less package pins are used and fewer solder joints and inter-chip conductors have to be fabricated.
Communication transceiver and protocol controller chips are an examples of electronic devices which commonly use one or more of these short haul serial bus for communicating between the internal, embedded controller and both on-chip and external devices. These types of transceiver and controller chips include interfaces which typically implement a single one out of several common short haul serial bus protocols such as Motorola""s Serial Peripheral Interface (SPI), National Semiconductor""s MicroWire, Philips Semiconductor""s Inter-IC (I2C) bus, and other similar vendor proprietary protocols. However, one disadvantage has been that the interface on such chips has been hard wired, thereby preventing it from being reprogrammed to use a different type of short haul serial bus protocol. The user of such a controller chip is simply limited to using the type of bus protocol which had been hard wired into the controller chip or else additional logic chips were required to translate between bus protocols, with a result of increased cost, size, and power consumption. Therefore, the external devices which communicated with the controller had the use the same type of serial bus protocol as had been hard wired into the controller chip. In many cases, this was a particular disadvantage because the other components of the electronic device may have been designed to implement a different type of protocol, or it may have been an advantage to use a different type of serial peripheral protocol with the external devices.
These and other considerations have given rise to the present invention.
The present invention has resulted, in significant part, from the discovery and recognition that a very substantial amount of I/O signal processing can be performed with a serial interface using a small set of relatively powerful, special purposse instructions and a reduced frequency of the clock used to execute those instructions. No more than two instructions need be executed for each time period during which bit signals are communicated to or from the interface. Many instructions provide the ability to perform multiple functions simultaneously, and the opportunity to execute two of these instructions during each time period of bit signal transmission and reception permits the opportunity to set up the necessary functionality in the interface for the transmission and/or reception of the bit signals and ancillary clock and control signals as may be necessary.
Of course, executing the instructions at reduced clock frequency reduces the amount of power consumed, because the power consumption is directly related to the clock frequency. Reducing the size and number of the instructions has the effect of reducing the size of the modules required to implement the interface, thereby facilitating its integration into a system on a chip or other ASSPs. The implementation of the interface is also directly enhanced by using digital logic circuit elements which minimize or avoid extra time clocks and time delays, while still minimizing the size of the interface.
The present invention also recognizes and resolves the issue of making short haul serial peripheral interfaces reprogrammable. Being re-programmable, each interface may be changed in functionality to implement different serial bus protocols by simply loading new instructions required for the protocols. Reprogrammability permits a range of generalities to be implemented in a system chip with an embedded processor, because the interface can be reprogrammed to implement any of the inter-chip serial bus protocols without restricting the bus protocol to a single hard wired implementation. Thus the previous restriction of using controllers and other system chips with only a single serial peripheral bus protocol is eliminated, which offers the advantage of allowing the user to select the most effective bus communication protocol for the elements within and exterior of the system chip. Avoiding this restriction permits the same system chip to execute different re-programmable firmware to support a variety of different serial bus protocols, allowing the functionality of the system chip to be updated with advancements in communication protocols.
These and other improvements are achieved in a function clock generator for generating a function clock signal used to clock the execution of instructions by an instruction decoder in a serial peripheral interface based on a source clock signal having one cycle per bit signal transmitted or received by the interface. The function clock generator comprises a logic gate circuit connected to receive the source clock signal and a delayed copy of the source clock signal. The logic gate circuit logically gates the source clock signal with a delayed copy of the source clock signal to create the function clock signal. A delay circuit receives the function clock signal and is responsive to edges of the function clock signal gated by the logic gate circuit to create the delayed copy of the source clock signal.
Other preferable aspects of the improvements involve the logic gate circuit gating one cycle of the function clock signal for each rising and falling edge of the source clock signal, making the frequency of the function clock signal twice the frequency of the source clock signal, time delaying the copy of the source clock signal through the through the delay circuit, implementing the logic gate circuit as XOR logic functionality by a plurality of NAND gates, and inverting the delayed copy of the source clock signal prior to applying the delayed copy of the source clock signal to the logic gate circuit. Preferably the time delay circuit includes a flip-flop, a delay element and an inverter connected in series and a feedback path from the inverter to the flip-flop to supply the signal from the inverter to the flip-flop in a feedback configuration, and the time delayed copy of the source clock signal is derived from an output signal from the inverter in the feedback path and the flip-flop is clocked to change states upon each rising edge of the function clock signal.
Other preferable aspects involve the function clock generator being responsive to an alternate inhibit signal in which they selective inverting logic gate is connected to receive the delayed copy of the source clock signal from the inverter of the delay circuit and to receive the alternate inhibit signal. The selective inverting logic gate supplies an inverted copy of the source clock signal from the delay circuit upon the assertion of the alternate inhibit signal, and the logic gate circuit responds to the source clock signal and the inverted copy of the source clock signal to transition edges of the function clock signal coincidentally with edges of the source clock signal. The transition of edges of the function clock signal occurs coincidentally with edges of the source clock signal so long as the alternate inhibit signal is asserted. The function clock generator may also be responsive to a rising edge primary signal to cause rising edges of both the function clock signal and the source clock signal upon the assertion of the alternate inhibit signal and the rising edge primary signal.
Other improved aspects of the present invention relate to a method for generating a function clock signal used to clock the execution of instructions in a serial peripheral interface based on a source clock signal having one cycle per bit signal transmitted or received by the interface. The method involves logically gating the source clock signal and a delayed copy of the source clock signal to create the function clock signal, and creating the delayed copy of the source clock signal used in response to edges of the function clock signal created by the logical gating. Many of the preferred functional aspects of this method have been described above in connection with the function clock generator.